1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with electrically rewritable nonvolatile memory cells.
2. Description of the Related Art
Recently, NAND-cell EEPROMs have been proposed as a type of highly integrated, electrically rewritable nonvolatile semiconductor memory devices (EEPROMs). The NAND-cell EEPROM is such that a plurality of memory cells of an n-channel FETMOS structure, each composed of a charge storage layer (e.g., a floating gate) and a control gate laid on an insulating film on the floating gate, are connected in series so as to share adjacent sources and drains and each series connection is determined to be a unit (a NAND cell) and connected to a bit line.
FIGS. 1A and 1B are a plan view and equivalent circuit diagram of a single NAND cell portion in a memory cell array, respectively. FIGS. 2A and 2B are sectional views taken along line 2A--2A and 2B--2B, respectively.
In a p-type silicon substrate 11 (or a p-well) enclosed by an isolation layer 12, a memory cell array composed of a plurality of NAND cells is formed. An explanation will be given, centering on a single NAND cell. In FIG. 1A, eight memory cells M1 to M8 are connected in series to form a NAND cell. Each memory cell is such that a floating gate 14 (14.sub.1, 14.sub.2, . . . , 14.sub.8) is formed above the substrate 11 via a tunnel insulating film 13 and above the floating gate, a control gate 16 (16.sub.1, 16.sub.2, . . . , 16.sub.8) is formed via an insulating film 15. A plurality of n-type diffusion layer 19, the sources and drains of these memory cells, are connected so that the memory cells may share the adjacent sources and drains, thereby connecting the memory cells in series.
At the drain side and source side of the NAND cell, there are provided first select gates 14.sub.9, 16.sub.9 and second select gates 14.sub.10, 16.sub.10 formed together with the floating gates and control gates of the memory cells. The substrate in which elements have been formed is covered with a CVD oxide film 17, on which a bit line 18 is provided. The control gate 16 of the NAND cell is provided in the form of control gates CG1, CG2, . . . , CG8. These control gate lines act as word lines. The select gates 14.sub.9, 16.sub.9 and 14.sub.10, 16.sub.10 are provided as select gates SG.sub.1, SG.sub.2 in succession in the row direction.
FIG. 3 is an equivalent circuit diagram of a memory cell array where NAND cells as described above are arranged in a matrix.
A source line is connected via a contact to a reference potential wire made of, for example, aluminum or polysilicon for every 64 bit line, for example. The reference potential wire is connected to a peripheral circuit. The control gates of the memory cells, first select gates and second select gates are provided consecutively in the row direction. Usually, a set of memory cells connected to a single control gate is called one page, and a group of pages sandwiched by a pair of the drain-side select gates (the first select gates) and that of the source-side select gates (the second select gates) is called one NAND block, or just one block.
The NAND-cell EEPROM operates as follows.
Program operation is effected, starting from the memory cell farthest from the bit line (that is, closest to the source line). A raised program voltage Vpp (=about 20 V) is applied to the control gate of the selected memory cell, an intermediate potential (=about 10 V) is applied to the control gates of the unselected memory cells and the first select gate, and either a 0 V ("0" programming) or the intermediate potential ("1" programming) is applied to the bit line, depending on the data. At this time, the potential of the bit line is transferred to the selected memory cell. In the case of data "0", a high voltage is applied between the floating gate of the selected memory cell and the substrate, causing electrons to be injected from the substrate into the floating gate by tunneling, causing the threshold voltage move in the positive direction. When the data is "1", the threshold voltage remains unchanged.
Erasing is effected in blocks almost at the same time. Specifically, all of the control gates and select gates in the blocks to be erased are placed at 0 V, and the raised potential VppE (about 20 V) applied to the p-well and n-type substrate is also applied to the control gates and select gates in the blocks not to be erased. This allows electrons in the floating gate to discharge into the well in the block to be erased, causing the threshold voltage to shift in the negative direction.
Reading is effected by placing the control gate of the selected memory cell at 0 V and the control gates of the other memory cells at the power supply voltage Vcc (e.g., 3 V) and sensing whether or not current flows in the selected memory cell. Since a plurality of memory cells are connected in columns in the NAND-cell EEPROM, a cell current in reading is small. Furthermore, since the control gates, first select gate, and second select gate are arranged consecutively in the row direction, a page of data is read onto the bit line simultaneously.
The NAND-cell EEPROM, however, has the following problems:
(1) A first problem is as follows. A single end-type sense amplifier is slow in reading. To realize what is called a high-speed reading folded bit line system used for DRAMs by using nonvolatile semi-conductor memory devices, the area of the cell array increases, resulting in an increase in the chip area. The reason for this will be described below. PA1 (2) A second problem is as follows. When the data extending over a plurality of pages is read, random reading is necessary at the time of switching the word line, leading to a waste of time, making the reading time longer. To solve this problem, the memory cell array and sense amplifiers may be divided into two to effect random reading and page reading simultaneously. With this method, however, the chip area will increase. The reason for this will be given below. PA1 (3) A third problem is as follows. When bit-line shielding that maintains every other bit line at a reference potential in a read operation is applied to a memory cell array of the open-bit line system or the single-end system to reduce noise stemming from the coupling capacitance between bit lines, because reading and writing are done on every other bit line, the unselected bit lines must be charged and discharged to an intermediate potential (about 10 V) for each cycle of programming and verify reading. Furthermore, in reading the data extending over a plurality of pages, the bit lines to be shielded at the time of page change must be discharged and the bit line to be selected next must be precharged. As a result, power consumption in a program operation and a read operation is great, and programming and reading get slower by the precharging time. The reason for this will be described below. PA1 (4) A fourth problem is as follows. PA1 (5) A fifth problem is as follows. PA1 (1) The second select MOS transistor in the first memory cell unit has a threshold voltage different from that of the first select MOS transistor in the second memory cell unit. PA1 (2) Timing means which performs the serial reading of the data stored in the other memory cell unit while performing the random reading of the data stored in one of the first and second memory cell units is further provided. PA1 (3) Potential applying means which applies a read select gate voltage to the first and second select MOS transistors in the subarray selected in such a manner that when the data in the first memory cell unit is read out, both of the first and second select MOS transistors in the first memory cell unit are made conducting and at least one of the first and second select MOS transistors in the second memory cell unit is made nonconducting, and when the nonvolatile memory section in the second memory cell unit is read from, at least one of the first and second select MOS transistors in the first memory cell unit is made nonconducting and both of the first and second select MOS transistors in the second memory cell unit are made conducting is provided. In this case, means for keeping the unselbit lines connected to the other memory cell unit at an unselected read bit-line potential when the data stored in one of the first and second memory cell units contained in the subarray are read out to the selected bit lines is further provided. Bit-line voltage sensing means for differentially sensing the difference between a first bit-line potential connected to the first memory cell unit and a second bit-line potential connected to the second memory cell unit in a read operation, by using the unselected read bit-line potential as a reference potential is still further provided. PA1 (4) The nonvolatile memory section is composed of a plurality of electrically rewritable nonvolatile memory cells. PA1 (5) The nonvolatile memory section is constructed in such a manner that a plurality of electrically rewritable nonvolatile memory cells, each cell made up of a charge storage layer and a control gate stacked one on top of the other on a semiconductor layer, connected in series so that adjacent memory cells may share the sources and drains. PA1 (6) Each of nonvolatile memory cells is composed of a charge storage layer and a control gate stacked one on top of the other on a semiconductor layer. The nonvolatile memory section is constructed in such a manner that at least one nonvolatile memory cell is connected in parallel so as to share all sources and drains. PA1 (7) A first, second, third, and fourth threshold voltages are selected by controlling impurities in the channel of a nonvolatile memory cell. PA1 (8) Each of a first and second select MOS transistors is composed of a charge storage layer and a select gate stacked one on top of the other on a semiconductor layer. PA1 (9) A first select MOS transistor and a second select MOS transistor differ from each other in gate length. PA1 (10) The device further comprises means for keeping the bit lines connected to the other memory cell unit at a constant potential in writing into one of the first and second memory cell units contained in the subarray and performing a verify operation to check to see if the programming has been done sufficiently or in performing a write, a program verify, a rewrite, and a program verify operation. PA1 (11) The memory cell array contains at least a first sub-memory cell array and a second sub-memory cell array, each of the first and second sub-memory cell arrays containing a first and a second memory cell unit, and the nonvolatile semiconductor memory device further comprising: means for applying a voltage applied to the gate of the first select MOS transistor in the first sub-memory cell array to the gate of the second select MOS transistor in the second sub-memory cell array and applying a voltage applied to the gate of the second select MOS transistor in the first sub-memory cell array to the gate of the first select MOS transistor in the second sub-memory cell array. PA1 (12) The connecting/disconnecting means contains a MOS transistor between the bit lines. PA1 (13) The bit line group is composed of the bit-line pairs connected to the same sense amplifier circuit. PA1 (14) The memory cell array is an open bit-line memory cell array where the sense amplifier is provided between bit lines. PA1 (15) The bit-line pairs containing at least two first bit lines (first bit line pair) and two second bit lines (second bit line pair) share the sense amplifier, the semiconductor memory device further comprising means for connecting the bit lines forming the second bit-line pair to each other in reading and programming the data from and into the memory cell connected to the first bit-line pair. PA1 (16) The first select MOS transistor has a threshold voltage different form that of the second select MOS transistor. PA1 (17) The memory cell unit contains at least a first memory cell unit and a second memory cell unit, the first and second memory cell units constituting a subarray in such a manner that they share the gate electrodes of the first and second select MOS transistors as a first and a second select gate, respectively, with the threshold voltage of the second select MOS transistor in the first memory cell unit being lower than the threshold voltage of the second select MOS transistor in the second memory cell unit when the threshold voltage of the first select MOS transistor in the first memory cell unit is higher than the threshold voltage of the first select MOS transistor in the second memory cell unit, and the threshold voltage of the second select MOS transistor in the first memory cell unit being higher than the threshold voltage of the second select MOS transistor in the second memory cell unit when the threshold voltage of the first select MOS transistor in the first memory cell unit is lower than the threshold voltage of the first select MOS transistor in the second memory cell unit. PA1 (18) The threshold voltage of the first select MOS transistor in the first memory cell unit is equal to the threshold voltage of the second select MOS transistor in the second memory cell unit, and the threshold voltage of the second select MOS transistor in the first memory cell unit is equal to the threshold voltage of the first select MOS transistor in the second memory cell unit. PA1 (19) The first memory cell units and the second memory cell units are arranged alternately to form the subarray. PA1 (1) The device comprises: a first and second common signal lines; at least one word line; and a memory cell array in which a plurality of memory cell units arranged in a matrix, each of the memory cell units containing a memory cell section having at least one nonvolatile memory cell and at least one select MOS transistor for making the memory cell section conducting to at least one of the first and second common signal lines; with this configuration, at one end of the memory cell units, a plurality of memory cell units sharing word line share a contact and are connected to the first common signal line; and the other end of the memory cell units shares a contact with at least one memory cell unit sharing word line and not sharing a contact with the one end of the memory cell units and is connected to the second common signal line. PA1 (2) The device comprises: a first and second common signal lines; at least one word line; and a memory cell array in which a plurality of memory cell units arranged in a matrix, each of the memory cell units containing a memory cell section having at least one nonvolatile memory cell and at least one select MOS transistor for making the memory cell section conducting to at least one of the first and second common signal lines; with this configuration, at one end of the memory cell units, a plurality of memory cell units sharing word line share a contact and are connected to the first common signal line; and the other end of the memory cell units shares a contact with at least one memory cell unit sharing word line and a contact with the one end of the memory cell units and is connected to the second common signal line. PA1 (3) The device comprises: a first and second common signal lines; at least one word line; and a memory cell array in which a plurality of memory cell units arranged in a matrix, each of the memory cell units containing a memory cell section having at least one nonvolatile memory cell and at least one select MOS transistor for making the memory cell section conducting to at least one of the first and second common signal lines; with this configuration, at one end of the memory cell units, a plurality of memory cell units sharing word line share a contact and are connected to the first common signal line; and the other end of the memory cell units shares a contact with at least one memory cell unit sharing word line and not sharing a contact with the one end of the memory cell units and at least one memory cell unit sharing a contact with one end of the memory cell units and are connected to the second common signal line. PA1 (1) The read unselected potential is the ground potential. PA1 (2) The program unselected potential is a power supply voltage or an in-chip power supply voltage. PA1 (3) The unselected gate voltage is negative. PA1 (4) The memory cell section is composed of electrically rewritable nonvolatile memory cells. PA1 (5) Each of nonvolatile memory cells is composed of a charge storage layer and a control gate stacked one on top of the other on a semiconductor layer. A plurality of memory cells are connected in series so that adjacent memory cells may share the sources and drains. PA1 (6) Each of nonvolatile memory cells is composed of a charge storage layer and a control gate stacked one on top of the other on a semiconductor layer. The nonvolatile memory cells are connected in parallel in such a manner that at least two memory cell shares all sources and drains. PA1 (7) The threshold voltages of a first to ninth select MOS transistors are made equal or different by making the channel impurity concentration equal or different.
FIG. 4 is a circuit diagram of a sense amplifier in a NAND-cell EEPROM.
The sense amplifier senses a bit-line potential as follows. First, when an address is set and the read mode turns on, a bit-line precharge control signal PREB changes from Vcc to Vss, thereby charging bit line BLj and node N2 to the power supply voltage Vcc. Furthermore, node N2 is placed at Vcc and node N1 is placed at Vss, resetting sense amplifier SA. After a word line has been selected, if the cell data is "0", the bit-line potential will be kept at Vcc; if the cell data is "1", the bit-line potential is discharged to Vss. After the potential of the bit line has been determined, the bit-line potential is transferred to node N2.
Next, select signals SENB1, SENB2 change from vcc to Vss and signals SEN1, SEN2 change from Vss to Vcc, thereby activating clocked inverter INV1. If the potential of node N2 is higher than the threshold voltage of clocked inverter INV.sub.2, node N1 is kept at Vss. If the potential of node N2 is lower than the threshold voltage of clocked inverter INV.sub.2, node N1 goes to Vcc and the potential of bit line BLj is sensed. Thereafter, clocked inverter INV.sub.2 is activated and the data is sensed and latched. When column select signal CSLj has changed from Vss to Vcc, the latched data is outputted to I/O, I/O'.
With the above method, the cell data is sensed, depending on whether the potential of the bit line in the floating state is higher or lower than the threshold voltage of the clocked inverter. The bit-line potential in the floating state varies with the state of adjacent bit lines, because of the capacitive coupling with adjacent bit lines. For example, when "0" data is programmed in the cell, a read current should not be allowed to flow and the potential of bit line BLj be kept at the precharge potential Vcc. On the other hand, when "1" data is programmed in the cell connected to the adjacent bit line BLi and a read current is allowed to flow, the potential of bit line BLi drops from Vcc to Vss. Then, the potential of bit line BLj supposed to remain at Vcc drops, being influenced by the potential of adjacent bit line BLi dropping from Vcc to Vss.
Therefore, to correctly sense that bit line BLj has "0" data on it, the threshold voltage of clocked inverter INV.sub.1 must be set rather low, taking into account changes in the bit-line potential due to the capacitive coupling between bit lines. To read "1" data from bit line BLi, the potential of bit line BLi must be dropped from Vcc to the threshold voltage of clocked inverter INV.sub.1. Taking into account the fact that the read current in the NAND cell is small, when the threshold voltage of clocked inverter INV.sub.1 is set rather low, it takes a longer time to sense the bit line.
In a sense amplifier using a clocked inverter as shown in FIG. 4, it take a long time to sense the bit-line potential. This will be described in numbers.
If the capacitance between adjacent bit lines accounts for 1/2 of the total capacitance of bit lines, bit line BLj supposed to remain at Vcc is dropped to Vcc/2 according to the voltage of BLi, provided that adjacent bit line BLi is at 0 V. For example, if the power supply voltage Vcc is 3 V, the voltage of bit line BLj is dropped to 1.5 V. Therefore, the threshold voltage of clocked inverter INV.sub.1 is set at, for example, 1.2 V, allowing a margin. The cell current when the read current in the NAND cell is the smallest (that is, when "1" is programmed in the selected cell and "0" is programmed in the series-connected unselected cells) is determined to be 1 .mu.A. If the capacitance of the bit line is 3 pF, discharging the potential of bit line BLi to the circuit threshold voltage requires: EQU 3 pF.times.(3-1.2)V/1.mu.A=5.4.mu.s
To solve the above problem, the folded bit-line system used for DRAMs may be used with a bit-line pair BLj,/BLj inputted to a sense amplifier, and the bit lines BLj,/BLj may be forced to operate differentially for high speed reading. As an example of reading the data from the cell connected to bit line BLj, the time required to discharge the bit line is estimated. If potential of bit line/BLj is kept at, for example, 1.5 V, and bit line BLj is precharged to 1.7 V, bit line BLj will remain at 1.7 V, provided that the information in the cell coupled to bit line BLj is "0", and the bit line will be discharged to 1.3 V, provided the information is "1". If the cell current 1 .mu.A and the bit-line capacitance is 3 pF, the time required to discharge the bit line will be: EQU 3 pF.times.(1.7-1.3)/1 .mu.A=1.2 .mu.s
This makes reading faster than in the conventional single end system.
In the folded bit-line system, when the cell coupled to bit line BLj is read from, bit line/BLj must not be discharged. With the conventional NAND-cell EEPROM, since the control gates of memory cells, the first select gate, and the second select gate are arranged consecutively in the row direction, when "1" is programmed in both of the cells coupled to adjacent bit lines BLj,/BLj, bit lines BLj,/BLj will be discharged simultaneously.
A method of not discharging bit line/BLj when the cell coupled to bit line BLj is read from may be, for example, a method of operating the select gates on the drain side (or the select gates on the source side) of bit line BLj and bit line/BLj with different timings. For example, to operate the drain-side select gate of bit line BLj and that of bit line/BLj with different timings, a control signal SGD.sub.1 to select the select gate of bit line BLj and a control signal SGD2 to select the select gate of bit line/BLj are required. When eight memory cells are assumed to be connected in series between the bit-line contact and the source line, the conventional cell array needs 10 wires (eight control gates and two select gates) for each block in the row direction. With this method, since 11 wires (eight control gates and three select gates) are needed, the cell array area increases, resulting in an increase in the chip area.
In the NAND-cell EEPROM, since memory cells are connected in series, the cell current is so small that it takes several .mu.s for the bit line to be discharged and about 10 .mu.s to complete random reading. A page of data is sensed and latched simultaneously. In page reading, because the latched data is just read out, it can be read in about 100 ns. For example, when the page length is 256 bytes and a page of data is read, a random read operation and 255 page read operations require: EQU 10+0.1.times.255 to 35 .mu.s
To read the data extending over a plurality of pages, the page switching section must effect a 10-.mu.s random read operation.
A method of reading pages of data with apparent page reading cycles without a random reading operation in changing the page includes, for example, a method of dividing the memory cell array and sense amplifiers into two to effect random reading and page reading simultaneously. While page reading is being done at one halved memory cell array, random reading is effected at the other halved memory cell array. This makes it possible to read the data extending over a plurality of pages, while maintaining the timing for page reading, without inserting a random reading operation at a point where pages change.
In this case, however, to effect random reading on the halved memory arrays with staggered timings, more peripheral circuits for applying a voltage to the word lines (e.g., a row decoder) must be needed. Since in the EEPROM, a high voltage of about 20 V is particularly applied to the word line in a program operation, the areas of transistors constituting the peripheral circuits (e.g., a row decoder) for applying a voltage to the word line are large. Therefore, when the conventional memory cell array employs the high-speed page reading method, use of more peripheral circuits (e.g., row decoders) for transmitting a voltage to the word line leads to an increase in the chip area.
As the memory device gets more highly integrated and the distance between bit lines gets shorter, the capacitive coupling between bit lines becomes greater. As a result, the potential of a bit lint supposed to remain high in reading is influenced by an adjacent bit line discharging to the low state and drops from the high to the low state. To reduce noise stemming from the capacitive coupling between bit lines, a method of keeping every other bit line at a constant potential in reading (bit-line shielding) has been proposed. In bit-line shielding, since reading is done on every other bit line, writing is also done on every other bit line.
In the open bit-line system and the single end system shown in FIG. 1A, since adjacent bit lines share select gates and control gates, when the cell data is read onto one bit line, the cell data is also read onto the adjacent bit line, with the result that the bit line discharges. Therefore, in using a method of keeping every other bit line at a reference potential to reduce noise stemming from the capacitive coupling between bit lines (bit-line shielding), the reference potential has to be at 0 V. As a result, when the data programmed over a plurality of pages is read (e.g., when the data in a memory cell connected to an odd-numbered bit line is read after the data in a memory cell connected to an even-numbered bit line has been read), the first read even-numbered bit line has discharged completely to 0 V and the second read odd-numbered bit line is precharged, starting at 0 V.
Specifically, at the time of page change in reading the data from a memory cell connected to an even-numbered bit line and then reading the data on an odd-numbered bit line, and at the time of page change in reading the data from a memory cell connected to an odd-numbered bit line and then reading the data on an even-numbered bit line, all of the previously read bit lines must be discharged and all of the bit lines to be read next has to be precharged, starting at 0 V. As described above, when bit-line shielding is applied to the open bit-line system or the single end system, using a conventional array, it takes time to precharge the bit lines at the time of page change in reading and the power consumption is large.
Explained next will be a problem arising in a read operation when bit-line shielding is applied to the open bit-line system or the single end system, using a conventional array.
When bit-line shielding is applied as described above, writing is also effected separately on a memory cell connected to an even-numbered bit line and a memory cell connected to an odd-numbered bit line. Therefore, for example, when the data is programmed into a memory cell connected to an even-numbered bit line, the data is not programmed into a memory cell connected to an odd-numbered bit line, so that an intermediate potential (about 10 V) is applied to the odd-numbered bit line. Namely, in a program operation, at least half of the bit lines must be charged to an intermediate potential.
In a program operation, first, writing is done and then, verify reading is done to check to see if the programming has been done sufficiently. Then, the cell sufficiently programmed into is not programmed into additionally, and only the insufficiently programmed cell is programmed into additionally. With the conventional memory cell array, when verify reading is effected after a memory cell connected to an even-numbered bit line has been programmed into, the odd-numbered bit line is also discharged from the intermediate potential. Therefore, for example, when a memory cell connected to an even-numbered bit line is programmed into, the odd-numbered bit line must be charged and discharged to the intermediate potential for each cycle of programming and verify reading, thus lengthening the writing time and increasing the power consumption.
In the NAND-cell EEPROM, the control gate of the memory cell selected in reading is placed at 0 V and the control gates of the other memory cells are placed at Vcc (e.g., 3 V), and then whether or not a cell current Icell flows is sensed. In this case, the amount of the cell current depends not only on the threshold voltage of the cell to be read from but also on the threshold voltages of all of the remaining cells connected in series.
In a case where eight memory cells are connected in series to form a NAND cell, Icell(Best), the largest Icell (the lowest resistance) is obtained when all of the threshold voltages of the eight cells connected in series are negative (in the "1" state). In a "1" read operation, Icell (Worst), the smallest Icell (the highest resistance) is obtained when "1" data is read from the memory cell (e.g., MC1 in FIG. 3) closest to the bit-line contact provided that the threshold voltages of all of the other cells connected in series with the cell to be read from are positive (in the "0" state).
The cell current flows from the bit line through the memory cells to the source line. In the conventional memory cell array, the source line is shared by a page of NAND cells to be read from simultaneously (FIG. 3). Here, consideration will be given to a case where the threshold voltages of the other 7 cells connected in series with the memory cell MC1 are positive (i.e., the cell current is the smallest Icell(Worst)) and the resistance of the other NAND columns sharing the source line is the lowest (i.e., the cell current is the largest Icell(Best)) when the memory cell farthest from the contact between the source line and the reference potential wire is read from (memory cell MC1 of FIG. 3). In this case, at the beginning of a read operation, a cell current flows from a low-resistance NAND column and the potential of the source line of the NAND cell to which the memory cell MC1 belong is I.times.R (where I is the cell current flowing at the beginning of reading and R is the resistance of the source line), because the resistance of the source line is high.
Specifically, because the sources of the memory cells in the NAND column containing the memory cell MC1 bounce from the ground potential Vss, the source-drain voltage and source-gate voltage in the memory cell drop, and the floating of the source from Vss causes the substrate bias effect, increasing the threshold voltage of the memory cell, with the result that the conductance of the memory cells in the NAND-cell column containing MC1 drops. As describe above, when the resistance of the source line is high, the source line bounces from the ground potential, making the cell current to flow less easily in the NAND column with a small cell current.
It is assumed that if the bit-line capacitance is C.sub.B and the threshold voltage of the memory cell is negative (i.e., in the "1" state), the bit-line potential must drop by .DELTA.V.sub.B from the precharge potential in order to effect reading. The maximum value of the bit-line discharging time T.sub.RWL is determined by the smallest cell current. When the source does not bounce, T.sub.RWL =C.sub.B /Icell(Worst) will be given. In the conventional memory cell, however, because the source line bounces, T.sub.RWL gets longer, lengthening the random accessing time. Furthermore, in the conventional NAND-cell EEPROM, to make the floating of the source line lower, a contact between the source line and the reference potential wire is provided for every 16 lines, for example. In this case, the area of the memory cell increases.
An increase in the bit-line discharging time due to the floating of the source line not only lengthens the reading time, but also causes variations in the threshold value programmed in the memory cells.
FIG. 5 shows the dependence of the bit-line discharging time on MCC1's threshold voltage in verify reading after "0" has been programmed into memory cell MCC1 of FIG. 6 (the threshold voltage of the memory cell is changed from a negative value to a positive value). In the verify reading of memory cell MCC1 of FIG. 6, because "0" has been programmed into the other memory cells MCC2, MCC3, MCC4, MCC5, . . . in the same page insufficiently as shown in FIG. 6 (i.e., they have a negative threshold value, not a positive threshold value), a large cell current flows, so that the source line bounces, lengthening the bit-line discharging time as shown in FIG. 5.
Therefore, when it is assumed that if the bit-line discharging time is equal to or longer than T.sub.BL1 at the time of verify reading, "0" has been programmed in the memory cell, because the source line bounces in the memory cell MCC1 of FIG. 6, it is judged that "0" has been programmed when the threshold voltage of the memory cell is equal to or larger than Vth1 of FIG. 5. On the other hand, when the cell current is large and the source does not bounce as in the memory cell MCD1 of FIG. 7, the bit-line discharging time is as shown in FIG. 5. Namely, when the data is programmed into memory cell MCD1, it is judged that "0" has been programmed if the threshold value of FIG. 5 is equal to or larger than Vthd1.
As described above, a variation of Vthd1-Vth1 in the threshold voltage takes place in memory cell MCC1 and memory cell MCD1. If the bit-line discharging time can be shortened by preventing the source line from floating and the bit-line discharging time of the memory cell MCC1 can be made as shown in FIG. 5, variations in the threshold value in the circuit can be made smaller (Vthd1-Vth2 of FIG. 5).
Furthermore, it is assumed that after memory cell MCC1 has been programmed into by a first write pulse and the threshold voltage (FIG. 8) has become Vth1, the memory cells MCC2, MCC3, MCC4, MCC5, . . . are brought into the "0" state by a second and later write pulses. Since programming into memory cell MCC1 has been completed by the first write pulse, memory cell MCC1 is not programmed into by the second and later pulses and the threshold value remains at Vth1.
As a result, because after the data has been programmed into the page of memory cells MCC1, MCC2, MCC3, . . . , a cell current does not flow through the memory cells MCC1, MCC2, MCC3, MCC4, MCC5, . . . in reading the data from memory cell MCC1, there is a possibility that the source line will not bounce and the bit-line discharging time will be shortened by .DELTA.T as shown in FIG. 8, and "1" will be read out. Specifically, because the data in the memory cells MCC2, MCC3, MCC4, . . . in the same page of memory cell MCC1 has changed by the second and later write pulses after memory cell MCC1 has been programmed into, the data in memory cell MCC1 in which "0" should have been programmed is read out as "1". The reason why the erroneous reading takes place is that when the memory cell is read from, the data in another memory cell influences the read current in the memory cell to be read from.
In the NAND-cell EEPROM, contacts between the drain-side select gates and the bit lines are provided adjacently as shown in FIG. 3. FIG. 9A shows an element area in a conventional memory cell array, including n-type diffusion layers, the source, gate, and drain regions of memory cells, and contacts (hereinafter, referred to as bit-line contacts) connecting the n-type diffusion layer to the bit lines (e.g., A1). In FIG. 9A, areas other than the shaded portions indicate element isolating areas between memory cells. In the Y-direction of FIG. 9A, NAND cells are connected in series. In the X-direction in FIG. 9A, n-type diffusion layers (source lines) and contacts between the memory cell array and bit lines are arranged. L' is the distance between bit-line contacts, L is the element isolation width between memory cells, and W is the channel width of the memory cell transistor.
In the conventional NAND cell array, even if the element isolating region width between memory cells is shortened, the pitch of memory cells in the column direction (the X-direction) cannot be shortened, because the bit-line contacts are arranged adjacently as seen from FIG. 9A. Namely, since the size in the X-direction is determined by the distance between bit-line contacts, L, the element isolation width L between memory cells is larger than the minimum element isolation width L0 determined by the field inversion withstand voltage between adjacent NAND cell columns and element isolation technology, resulting in an increase in the area of the memory cell array.
Furthermore, as shown in FIG. 9B, an allowance 1 for the contact and the element region must be made smaller according to a reduction in the memory cell pitch. With a smaller allowance 1, however, there is a possibility that misalignment will permit a contact to be shifted and formed on an element isolation, short-circuiting a well or a substrate in which bit lines and memory cells are formed.
As described above, with the conventional EEPROM, because the source line bounces from the ground potential when the resistance of the source line is high, the bit-line discharging time get longer and the random access time is lengthened. Furthermore, when a contact between the source line and a reference potential wires is provided for every 16 lines, for example, the area for the memory cells increases.
Furthermore, since bit-line contacts are arranged adjacently, the memory cell pitch in the column direction cannot be shortened. Additionally, an allowance for the alignment of the contact with the element area must be made smaller according to a reduction in the memory cell pitch. A smaller allowance can cause misalignment, which may permit a contact to be shifted and formed on an element isolation, thus short-circuiting a well or a substrate in which bit lines and memory cells are formed.